The present invention relates generally to semiconductor fabrication techniques and devices thereof. The present invention also relates to MIM structures and devices thereof. The present invention additionally relates to recesses formed on MIM structures. The present invention also relates to methods and devices for avoiding breakdown and leakage in MIM structures. The present invention additionally relates to damascene processes and devices thereof.
Metal-insulator-metal fabrication technology is widely used in the fabrication of semiconductor integrated circuit devices. Metal-insulator-metal (MIM) capacitors, for example, are commonly utilized in high performance applications of CMOS technology. A typical MIM capacitor possesses a sandwich structure that can generally be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating layer. Both parallel plates are conventionally made from Al or AlCu alloys. These metals are patterned and etched needing several photolithography photo masking steps. The thin insulating dielectric layer is usually made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD).
Such MIM capacitors are generally utilized in semiconductor devices, such as integrated circuits (ICs) for storing an electrical charge. In ICs, such as dynamic random access memory (DRAM), capacitors are used for storage in the memory cells. Typically, capacitors formed in ICs include a lower electrode made of, e.g., polycrystalline silicon (polysilicon), a dielectric layer made of, e.g., tantalum pentoxide and/or barium strontium titanate, and an upper electrode made of, e.g., titanium nitride, titanium, tungsten, platinum or polysilicon.
MIM capacitors can be formed utilizing damascene fabrication technology, which well known in the semiconductor fabrication arts. The damascene processing is a xe2x80x9cstandardxe2x80x9d method for fabricating planar copper interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners, underlying diffusion barriers, have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
Note generally that the term xe2x80x9cdamascene processxe2x80x9d or xe2x80x9cdamascene processesxe2x80x9d is utilized herein to refer to a standard semiconductor fabrication processes. In the processing sequence known in the art as the xe2x80x9cDamascene Processxe2x80x9d, a dielectric layer can be patterned using known techniques such as the use of a photoresist material, which is exposed to define the wiring pattern. After developing, the photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. This is generally termed a lithography or photolithography process or operation and may be used for both additive or subtractive metallization procedures as is known in the art.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses (i.e., recesses) can be formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes.
Next, wire metallization layers can be deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
Another metal deposition technique, besides the aforementioned sputtering techniques, has been adapted as a standard for copper metallization. This technique is referred to generally as the electrochemical deposition (ECD) of copper. The electrochemical copper deposition (ECD) requires, e.g., sputtering techniques, physical vapor deposition (PVD), to deposit thin underlying diffusion barrier film (Ta, TaN) and a conductive xe2x80x9cseedxe2x80x9d layer of copper.
One of the primary problems encountered during MIM fabrication processes, particular copper damascene processes, involves the formation of recesses or film notches during device fabrication. For example, recesses between TaN and copper interfaces in MIM devices following copper CMP can lead easily to MIM breakdown and leakage due to the presence of such recesses. In an oxide layer of an MIM device, for example, a recess can lead to breakdown of the oxide layer. The present inventors have thus concluded based on the foregoing that a need exists for an apparatus and method which can effectively prevent the formation of such recesses. The present invention disclosed herein addresses this important need.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an improved semiconductor fabrication method and apparatus.
It is yet another aspect of the present invention to provide an improved metal-insulator-metal (MIM) fabrication method and apparatus.
It is still another aspect of the present invention to provide an improved MIM device structure that avoids breakdowns and leakages associated with damascene copper processes.
It is also an aspect of the present invention to provide an MIM capacitor which is formed based on an extra pattern in which an outer top electrode area is removed to avoid overlapping of a recessed bottom electrode area to achieve a final MIM capacitor structure.
The above and other aspects of the present invention can thus be achieved as is now described. A method and apparatus are disclosed herein for forming a metal-insulator-metal device that avoids breakdown and leakage due to semiconductor damascene copper fabrication processes associated with the formation of the metal-insulator-metal device. An extra pattern may be defined for forming a metal-insulator-metal device to remove an outer top electrode area associated with the metal-insulator-metal device and avoid recesses in an insulating layer thereof.
The metal-insulator-metal device is thus generally formed without the outer top electrode area, such that an area previously associated with the outer top electrode area overlaps a recessed bottom electrode area of the metal-insulator-metal device to achieve a final metal-insulator-metal device structure that avoids breakdown and leakage as a result of associated damascene copper processes. Essentially, an initial pattern may be defined for forming the metal-insulator device, and thereafter the extra pattern can be defined.
The metal-insulator-metal device generally can comprise metal-insulator-metal capacitor. The metal-insulator-metal device can be formed utilizing at least one TaN layer and at least one copper layer. A first TaN layer may be deposited upon a substrate followed by a dielectric layer upon the substrate to form the metal-insulator-metal device and a second TaN layer to form the metal-insulator-metal device.
The extra pattern described herein can be generally defined to remove only the outer top electrode area associated with the metal-insulator-metal device. Such an extra pattern can also be defined to remove at least one film notch associated with the formation of the metal-insulator-metal device. Finally, the extra pattern can be defined to remove at least one recess associated with the formation of the metal-insulator-metal device. The extra pattern is thus defined to remove the outer top electrode area only, wherein the area overlaps the recessed bottom electrode area. Formation of the capacitor is thus controlled at the area where a recess profile is not included, thereby avoiding MIM structure breakdown and leakage.